Integrated circuits of semiconductor memory devices may receive and/or transmit digital signals including data with a logic “1(high)” level and/or a logic “0(low)” level. Thus, integrated circuits may include a receiving circuit for accepting data and/or a transmitting circuit for outputting data.
In general, a receiving circuit may receive input data in synchronization with a clock signal having a clock pulse and may discriminate whether the input data has a logic “1” level or a logic “0” level. In order that the receiving circuit to correctly determine the logic level of the input data, the clock pulse of the clock signal may occur at the middle of a period for which the input data is input. That is, when the clock pulse of the clock signal occurs at the middle of the period for which the input data is input, the receiving circuit may have a sufficient margin to accurately discriminate the logic level of the input data with a smaller number of errors.
In some cases, the clock pulse of the clock signal may not occur at the middle of the activation period of the input data due to a skew between the input data and the clock signal. In such a case, the receiving circuit may erroneously discriminate the logic level of the input data to cause errors.